PCI-SIG released version 0.5 of the PCI-Express 7.0 specification to its members this week, the second draft of the specification and the final call for PCI-SIG members to submit new features to the standard. PCI-SIG used the latest update to reiterate that development of the new standard remains on track for a final version in 2025.

PCIe 7.0 is the next generation of computer interconnect technology, designed to increase data transfer speeds to 128 GT/s per pin, double the 64 GT/s of PCIe 6.0 and quadruple the 32 GT/s of PCIe 5.0. This will allow a 16-lane (x16) connection to support 256 GB/s of bandwidth in each direction simultaneously (excluding encoding overhead). Such speeds will be very convenient for future data centers as well as artificial intelligence and high-performance computing applications that require faster data transfer rates, including network data transfer rates.

To achieve the impressive data transfer rates, PCIe 7.0 doubles the bus frequency of the physical layer compared to PCIe 5.0 and 6.0. In addition to this, the standard retains the pulse amplitude modulation with four-level signaling (PAM4), 1b/1b FLIT mode encoding, and forward error correction (FEC) technology that has been used in PCIe 6.0. In addition to this, PCI-SIG said that the PCIe 7.0 specification also focuses on enhanced channel parameters and coverage as well as improved power efficiency.

Overall, the engineers behind PCIe 7.0 have their work cut out for them, given that it requires doubling the bus frequency of the physical layer, a major development that PCIe 6.0 sidestepped with PAM4 signaling. Nothing comes for free when it comes to improving data signaling, and with PCIe 7.0, the PCI-SIG is arguably back in hard-mode development, as the physical layer needs to be improved once again—this time to enable it to operate at around 30GHz. It remains to be seen, though, how much of the heavy lifting will be done through smart signaling (and retimers) and how much will be done through pure material improvements, such as thicker printed circuit boards (PCBs) and low-loss materials.

The next major step for PCIe 7.0 is to finalize version 0.7 of the specification, which is considered a full draft where all aspects must be fully defined and the electrical specifications must be verified with test chips. New features cannot be added after this iteration of the specification is released. PCIe 6.0 eventually went through 4 major drafts, 0.3, 0.5, 0.7, and 0.9, so PCIe 7.0 is likely on the same track.

It should take several years for the first PCIe 7.0 hardware to hit shelves once it is finalized in 2025. While work is already underway on controller IP and initial hardware, the process extends well beyond the release of the final PCIe specification.

PCI-SIG said in this release that the PCIe 7.0 specification is still on track for full release in 2025. The PCIe 7.0 specification includes the following functional goals:

1. Provides 128 GT/s raw bit rate and up to 512 GB/s bidirectional bit rate in x16 configuration;

2. Utilize PAM4 (4-level pulse amplitude modulation) signaling;

3. Pay attention to channel parameters and reach;

4. Continue to achieve low latency and high reliability goals;

5. Improve power efficiency;

6. Maintain backward compatibility with all previous generations of PCIe technology;

PCIe 7.0 technology is designed to be a scalable interconnect solution for data-intensive markets such as 800G Ethernet, AI/ML, hyperscale data centers, HPC, quantum computing, and cloud. As PCIe technology continues to evolve to meet the high-bandwidth demands of these applications, the PCIe 7.0 architecture will focus on channel parameters and reach while improving power efficiency.

As mentioned above, in June last year, PCI-SIG released version 0.3 of PCIe 7.0.

PCIe 7.0 targets version 0.3

Early work on PCIe 7.0 began in 2022. At the PCI-SIG Developer Conference that year, PCI-SIG announced the specification of PCI Express (PCIe) 7.0.

"For 30 years, the guiding principle of the PCI-SIG has been 'If we build it, they will come,'" said Nathan Brookwood, Fellow at Insight 64. "Early parallel versions of PCI technology accommodated hundreds of megabytes/second, ideally suited to the graphics, storage and networking needs of the 1990s. In 2003, the PCI-SIG evolved to a serial design supporting gigabyte/second speeds to accommodate faster solid-state disks and 100MbE Ethernet. Almost like clockwork, the PCI-SIG has doubled the bandwidth of the PCIe specification every three years to meet the challenges of emerging applications and markets. The PCI-SIG has now announced plans to double the lane speed to 512 GB/s (bidirectional), which will put it on track to double the PCIe specification performance in another 3-year cycle."

“With the upcoming PCIe 7.0 specification, PCI-SIG continues our 30-year commitment to delivering industry-leading specifications that push the boundaries of innovation,” said Al Yanes, PCI-SIG president and chairman. “As PCIe technology continues to evolve to meet high-bandwidth demands, our working group’s focus will be on lane parameters and ranges, as well as improving power efficiency.”

The PCIe 7.0 specification is designed to support emerging applications such as 800G Ethernet, AI/ML, cloud and quantum computing; as well as data-intensive markets such as hyperscale data centers, high-performance computing (HPC) and military/aerospace.

By the 2023 meeting, PCI-SIG had completed the first draft of the specification, version 0.3, and was ready to distribute it to the organization’s members, marking the next step in the development of the standard.

Early drafts of PCI-SIG standards tend to focus less on public technical details, and PCIe 7.0 v0.3 is no exception in this regard.

Still, the completion of the first draft of the specification is important because it shows that the group has successfully developed the core technical foundations needed for faster PCIe communications. This was no easy feat, as PCIe 7.0 requires doubling the bus frequency of the physical layer, a major development that PCIe 6.0 sidestepped with PAM4 signaling. Even so, nothing comes for free when it comes to improving data signaling, but with PCIe 7.0, the PCI-SIG is arguably back in hard-mode development, as the physical layer needs to be improved once again—this time to enable it to operate at around 30GHz.

On the electrical side, PCIe 7.0 sticks with PAM4 + FLIT encoding, just like its predecessor, so the next standard will save a lot of money on physical layer development by focusing on logical layer development.

Ultimately, PCI-SIG's standards cadence is based on a three-year development cycle. Therefore, this year's draft announcement is on schedule for the group, which expects to have another two years of development time. Assuming the remaining draft work goes smoothly, PCI-SIG expects to finalize the PCIe 7.0 specification in 2025.

In turn, the specification's compliance program should be up and running by 2027. The compliance program is a functional barometer of hardware availability, as compliance testing and certification are actually necessary before any large commercial hardware using the new specification can ship. With very few exceptions, these tend to take 2 to 2.5 years to complete. All of this means that the first commercial PCIe 7.0 products are not expected to launch until at least 2027 (five years from now), highlighting that there is still a lot of work to be done on PCIe 7.0 after the initial draft.

While PCIe 7.0 is in development, hardware for PCIe 6.0 is still in development, and even PCIe 5.0 devices have only been available for a short time. So while the core specification is being developed, the PCI-SIG is also working on completing some ancillary areas of the specification, especially cabling.

While we traditionally think of PCIe as a bus that was routed through a printed circuit board first, the standard has always allowed for cabling. With the introduction of the new standard, the PCI-SIG actually expected the use of cabling in servers and other high-end equipment to grow, as PCBs have limited channel range, and this gets worse as signal frequencies increase. Therefore, as new technologies and materials are creating new options for better cables, cables are being given a new look as an option to maintain/extend channel range according to the latest standards.

To this end, PCI-SIG is developing two cabling specifications that are expected to be released in the fourth quarter of this year. The specification will cover PCIe 5.0 and PCIe 6.0 (because the signal frequency does not change), as well as specifications for internal and external cables. Internal cabling connects devices to other parts within the system (devices and motherboards/backplanes), while external cabling will be used for system-to-system connections.

PCI Express is about a generation behind Ethernet in terms of signaling technology and absolute signaling rates. This means that much of the initial development of high-speed copper signaling had already been addressed by the Ethernet working group. So while some work still needed to be done to adapt these technologies to PCIe, the basic technology had already been proven, which helped to simplify the development of the PCIe standard and cabling a little.

All in all, the cable development is clearly more of a server use case for the technology than what we’ve seen in the consumer space. But cabling standards are still an important development for these use cases, especially as companies continue to stitch together more powerful systems and clusters.

The future of PCIe, using optical technology

Today's computers rely heavily on the PCI Express bus to make everything work, and it does a great job of meeting our need for high-bandwidth connections between all of our components. However, demands continue to increase, and the PCI-SIG group that develops these standards is always looking ahead to stay ahead.

While it’s currently working on technologies like PCIe 6.0 and 7.0, it’s also looking further into the future, with news that it has convened a working group to explore a radical shift toward optical interconnects rather than the electrical ones it has traditionally used.

In August 2023, PCI-SIG announced the creation of a new working group to deliver PCI Express (PCIe ) technology over optical connections. The PCI-SIG Optical Working Group is designed to be optical technology agnostic, supporting a wide range of optical technologies while potentially developing technology-specific form factors.

“Optical connections will be an important advancement for PCIe architecture as they will enable higher performance, lower power consumption, longer range and lower latency,” said Nathan Brookwood, a fellow at Insight 64. “Many data-hungry markets and applications such as cloud and quantum computing, hyperscale data centers and high-performance computing will benefit from a PCIe architecture that leverages optical connections.”

“We are seeing strong industry interest in expanding the reach of the established, multi-generation, energy-efficient PCIe technology standard by enabling optical connectivity between applications,” said Al Yanes, PCI-SIG president and chairman. “PCI-SIG welcomes industry input and invites all PCI-SIG members to join the Optical Working Group, share their expertise and help shape specific working group goals and requirements.”

While the existing PCI-SIG working group will continue to move toward 128GT/s data rates in the PCIe 7.0 specification, this new optical working group will focus on making the PCIe architecture more optically friendly.

First released in 2000, PCI-Express was originally developed around the use of high-density edge connectors, which are still in use today. The PCIe Card Electromechanical Specification (CEM) defines the PCIe add-in card form factor used for the past two decades, ranging from x1 to x16 connections.

While the PCIe CEM has remained virtually unchanged for many years (largely to ensure backward and forward compatibility), the signaling standard itself has undergone multiple speed upgrades. Including the latest PCIe 6.0 standard, the speed of a single PCIe lane has increased 32 times since 2000, and the PCI-SIG will double that speed again with PCIe 7.0 in 2025. Due to the huge increase in the amount of data transmitted per pin, the actual frequency bandwidth used by the standard has increased by a similar amount, with PCIe 7.0 set to run at nearly 32GHz.

When developing newer PCIe standards, the PCI-SIG worked to minimize these issues, such as using alternative signaling methods that didn’t require higher frequencies (such as PCIe 6 with PAM-4), and using mid-range retimers as materials improved to help keep up with the higher frequencies used by the standard. But the frequency limitations of copper traces within PCBs have never been completely eliminated, which is why in recent years the PCI-SIG has created an official standard for PCIe based on copper wiring.

The PCIe 5.0/6.0 cabling standard, still under work through the end of this year, provides the option of using copper cables to transmit PCIe both within a system (internal) and between systems (external). In particular, relatively thick copper cables have less signal loss than PCB traces, overcoming the immediate drawback of high-frequency communications, which is short channel reach (i.e., short signal propagation distance). While the cabling standard is intended as a replacement for PCIe CEM connectors rather than a wholesale replacement, its existence highlights the problems facing high-frequency signal transmission over copper cables, a problem that will only become more challenging once PCIe 7.0 becomes available.

This is what led to the formation of the PCI-SIG Optical Working Group. Like the Ethernet community, which is often at the forefront of high-frequency signaling innovation, PCI-SIG sees light-based optical communications as part of the future of PCIe. As we have seen with optical networking technology, optical communications have the potential for longer distances and higher data rates as light frequencies increase dramatically, and lower power consumption compared to increasingly power-hungry copper wire transmission. For these reasons, PCI-SIG is forming an Optical Working Group to help develop the standards needed to deliver PCIe over optical connections.

Strictly speaking, driving PCIe over optical connections does not require the creation of a new optical standard. Several vendors already offer proprietary solutions that focus on external connections. But optical standards were created to do exactly that — standardize how PCIe over fiber works and behaves. As part of the working group announcement, the traditionally consensus-based PCI-SIG made it clear that they will not be developing the standard for any single optical technology, but rather aim to make it technology-agnostic, allowing the specification to support a wide range of optical technologies.

But PCI-SIG's relatively broad announcement doesn't stop at replacing current copper cables with optical cables, the group is also considering "potential development of technology-specific form factors." While the classic CEM connector is unlikely to completely disappear anytime soon (backward and forward compatibility is very important), the CEM connector is the weakest/hardest way to deliver PCIe today. So if PCI-SIG is considering new form factors, it's likely that the optical working group will at least consider some kind of optical-based successor to CEM. If this actually comes to pass, it would easily be the biggest change in the 23-plus year history of the PCIe specification.

But it’s a safe bet that any such change, if it happens, will be years away. The new optical working group hasn’t even been formed yet, let alone had its goals and requirements set. The group’s broad remit, aimed at making PCIe more optically friendly, is several years away from having any impact—presumably no sooner than developing cabling standards for PCIe 7.0, if not more directly on the PCIe 8.0 spec. But it’s indicative of how PCI-SIG leadership feels about the future development of the PCIe standard, assuming they can get consensus from the membership. And, while it’s not explicitly stated in the PCI-SIG press release, any serious use of optical PCIe in this way would appear to be based on cheap optical transceivers (i.e., silicon photonics).

Regardless, it will be interesting to see what PCI-SIG’s new optical working group ultimately produces. As PCIe begins to approach the practical limits of copper, the future of the industry-standard peripheral interconnect may well be moving toward lightweight.